1. Field of the Invention
The disclosed invention relates to solid-state image sensors and more specifically to small pixel size CMOS image sensors that have global shutter (GS) and rolling shutter (RS) capabilities.
2. Description of Related Art
Typical image sensors sense light by converting impinging photons into electrons that are integrated (collected) in the sensor pixels. After completion of the integration cycle collected charge is converted into a voltage, which is supplied to the output terminals of the sensor. In CMOS image sensors the charge to voltage conversion is accomplished directly in the pixels themselves and the analog pixel voltage is transferred to the output terminals through various pixel addressing and scanning schemes. The analog signal can also be converted on-chip to a digital equivalent before reaching the chip output. The pixels have incorporated in them a buffer amplifier, typically a Source Follower (SF), which drives the sense lines that are connected to the pixels by suitable addressing transistors. In some designs the SF itself may also be used in an addressing function. After charge to voltage conversion is completed and the resulting signal transferred out from the pixels, the pixels are reset in order to be ready for accumulation of new charge. In pixels that are using Floating Diffusion (FD) as the charge detection node, the reset is accomplished by momentarily turning on a reset transistor that conductively connects the FD node to a voltage reference, which is typically the pixel drain node. This step removes collected charge; however, it generates kTC-reset noise as is well known in the art. The kTC noise has to be removed from the signal by the Correlated Double Sampling (CDS) signal processing technique in order to achieve the desired low noise performance. The typical CMOS sensors that utilize the CDS concept usually require at least three or four transistors (4T) in the pixel. An example of the 4T pixel circuit with pinned photodiode can be found in the U.S. Pat. No. 5,625,210 to Lee, which patent is incorporated herein by reference.
In modern CMOS sensor designs the circuitry for several photodiodes may be shared as can be found for example in U.S. Pat. No. 6,657,665 B1 to Guidash, which patent is also incorporated herein by reference. In this patent the pixel consists of two photodiodes located in the neighboring rows that share the same circuitry. Such shared circuit concept can result in having fewer metal bus lines in the row direction and column direction per photodiode. The circuit sharing is very useful for designing small pixels or pixels with high Fill Factor (FF) since the spacing and the width of the metal lines essentially determines the minimum pixel size.
The principal disadvantage of the standard CMOS sensors is that the pixel scanning, after charge has been accumulated in them, is performed in a sequential manner row by row. This generates the exposure time skew, which can be observed in the pictures of moving object and which causes an undesirable picture distortion. This method of CMOS sensor scanning is called the “rolling shutter” mode and it resembles the action of the focal plane slit shutter in the old photographic film cameras. In most applications, however, it is preferable to expose all the pixels of the image at the same time without the skew and thus eliminate the distortion of moving objects. This type of sensor operation is called the “global shuttering”, which resembles the operation of a mechanical iris shutter in the old film cameras. In order to implement this kind of global shuttering it is necessary to provide another charge storage site in the pixels. After charge is integrated in the photodiodes of the pixels it is transferred to the pixel storage sites simultaneously in all the pixels of the array where it can wait for the scanning in the row by row fashion. The pixel scanning time skew is thus independent of the frame pixel exposure time. There have been several methods published in the literature how to incorporate additional charge storage sites into the CMOS sensor pixels. The recent publication described in: ISSCC Digest of Technical Papers pp. 398, 399, by Keita Yasutomi, Shinya Itoh, Shoji Kawahito entitled: “A 2.7e Temporal Noise 99.7% Shutter Efficiency 92 dB Dynamic Range CMOS Image Sensor with Dual Global Shutter Pixels”, is a modification of the well known Interline Transfer CCD concept where charge from the pixel photodiodes is transferred first into vertical CCD registers located in the space between the pixels and then from there transferred in parallel fashion row by row into the serial register followed by the CCD transfer out into the common single amplifier. The application of the CCD charge transfer concept into a CMOS sensor to implement the global shutter is shown in FIG. 1.
The drawing 100 in FIG. 1 represents the simplified cross section of a pixel of the CMOS sensor that has the global shuttering capability. After charge integration is completed in a pinned photodiode 101 charge is transferred via the transfer gate transistor 103 into the second pinned photodiode 102 where it waits for scanning. The charge transfer from the first to the second pinned diode is completed in a CCD fashion without generating any kTC noise. It is also necessary that the second pinned photodiode has a higher pinning voltage than the first pinned photodiode or the transfer gate 103 has a potential barrier 104 and a well 105 incorporated in it. It is also necessary that the charge storage pinned photodiode 102 is well shielded from the impinging photons to prevent undesirable smear effects when the objects in the scene move. The signal charge readout from the second pinned photodiode 102 then proceeds in the standard way by first resetting the Floating Diffusion (FD) node 106 to the drain bias voltage by momentarily turning on the reset transistor followed by pulsing the charge transfer transistor gate 107. The PD 101 can also be reset by turning on the anti-blooming reset gate (AB) 108 thus allowing the collected charge to flow out into the drain 109. During the charge integration time the AB reset gate bias is adjusted such that, for the pixels with maximum illumination, charge overflows the barrier 110 and flows into the drain thus preventing spreading into the neighboring pixels. The pixel readout sequence in this device can now proceed in a sequential order row by row. The signal appearing of the FD is buffered by the standard source follower transistor. Using the pinned photodiodes for charge storage is advantageous since it is well known that these diodes have a low dark current generation. The high dark current in the storage sites would add to noise and also would generate undesirable shading effects in the picture that would have to be compensated for. Unfortunately, the second pinned photodiode consumes a significant amount of valuable pixel area, thus increasing the size of the sensor and ultimately its cost. This concept also consumes a large amount of the voltage budget that is available for the pixel operation. It is thus desirable to investigate other possibilities of how to build the CMOS sensors with the global shuttering capability that consumes less pixel area do not sacrifice the pixel performance and operate with low voltages.